PIC16F723A-I/SS【PDF 67/286 页】MCU PIC 7KB FLASH XLP 28-SSOP

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2010-2012 Microchip Technology Inc.

DS41417B-page 159

PIC16(L)F722A/723A

17.1.2

SLAVE MODE

For any SPI device acting as a slave, the data is

transmitted and received as external clock pulses

appear on SCK pin. This external clock must meet the

minimum high and low times as specified in the

electrical specifications.

17.1.2.1

Slave Mode Operation

The SSP consists of a transmit/receive shift register

(SSPSR) and a buffer register (SSPBUF). The SSPSR

shifts the data in and out of the device, MSb first. The

SSPBUF holds the data that was written to the SSPSR

until the received data is ready.

The slave has no control as to when data will be

clocked in or out of the device. All data that is to be

transmitted, to a master or another slave, must be

loaded into the SSPBUF register before the first clock

pulse is received.

Once eight bits of data have been received:

Received byte is moved to the SSPBUF register

BF bit of the SSPSTAT register is set

SSPIF bit of the PIR1 register is set

Any write to the SSPBUF register during transmission/

reception of data will be ignored and the Write Collision

Detect bit, WCOL of the SSPCON register, will be set.

User software must clear the WCOL bit so that it can be

determined if the following write(s) to the SSPBUF

The user’s firmware must read SSPBUF, clearing the

BF flag, or the SSPOV bit of the SSPCON register will

be set with the reception of the next byte and

communication will be disabled.

A SPI module transmits and receives at the same time,

occasionally causing dummy data to be transmitted/

received. It is up to the user to determine which data is

to be used and what can be discarded.

17.1.2.2

Enabling Slave I/O

To enable the serial port, the SSPEN bit of the

SSPCON register must be set. If a Slave mode of

operation is selected in the SSPM bits of the SSPCON

as serial port pins.

For these pins to function as serial port pins, they must

have their corresponding data direction bits set or

cleared in the associated TRIS register as follows:

SDI configured as input

SDO configured as output

SCK configured as input

Optionally, a fourth pin, Slave Select (SS) may be used

in Slave mode. Slave Select may be configured to

operate on one of the following pins via the SSSEL bit in

the APFCON register.

RA5/AN4/SS

RA0/AN0/SS

Upon selection of a Slave Select pin, the appropriate

bits must be set in the ANSELA and TRISA registers.

Slave Select must be set as an input by setting the

corresponding bit in TRISA, and digital I/O must be

enabled on the SS pin by clearing the corresponding bit

of the ANSELA register.

17.1.2.3

Slave Mode Setup

When initializing the SSP module to SPI Slave mode,

compatibility must be ensured with the master device.

This is done by programming the appropriate control

bits of the SSPCON and SSPSTAT registers. These

control bits allow the following to be specified:

SCK as clock input

Idle state of SCK (CKP bit)

Data input sample phase (SMP bit)

Output data on rising/falling edge of SCK (CKE bit)

Figure 17-4 and Figure 17-5 show example waveforms

of Slave mode operation.

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